Special report on die-to-die interconnect standards; chiplet development flows; AI accelerators move out from data centers; optimizing analog; UALink; power intent; HBM4.

They depend on careful coordination between RTL, verification and implementation teams. And here’s where things get tricky. Without a consis­tent way to describe and validate power intent across the ...

Two standards — Bunch of Wires (BoW) and UCIe — compete with proprietary designs. Today, the latter predominates, since ...

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has ...

Structural and Thermal Aware Methodology for Placement in 2.5D Integration” was published by researchers at Pennsylvania ...

A new technical paper titled “Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor” ...

An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications” was published by researchers at EPFL.

Just adding more or thicker wires to a design isn't sufficient with chiplets.

High-voltage PCB spacing; HBM4; AI changes engineering teams; ion beam etching; wafer market and raw materials.

Benchmarking 3D-IC cooling; rad-hard flip-flops; high-speed data error correction. Researchers from Massachusetts Institute ...

AI export rule to be scrapped; SEMI, EU request; Cadence, Nvidia supercomputer; AI co-processor; Imagination's new GPU; semi ...

Supply chain vulnerabilities, hardware attacks, and communications hacks are rife. Autonomous technology poses extra threats.